1. Field of the Invention
The present invention relates to semiconductor memory devices and, in particular, to systems and methods for generating data strobe signals for use in accessing data from dynamic random access memory devices.
2. Discussion of Related Art
The increase in computing speeds of modern computing systems has created a demand for developing high speed memory devices. Due to increasing memory speed requirements, a parallel path (i.e. stub bus) memory architecture currently proves impracticable to implement. Accordingly, memory architectures utilizing fully buffered dual in-line memory modules (“FB-DIMM”) are commonly used.
FB-DIMM include an array of dynamic random access memory (“DRAM”) modules coupled to an advanced memory buffer (“AMB”). A memory controller is serially interfaced with the AMB. Data transfers (e.g. data reads/writes) to the DRAM are commonly performed via the AMB in parallel utilizing a double-data rate two (“DDR2”) source-synchronous dynamic random access memory (“SDRAM”) architecture. In DDR2 implementations, data transfers are synchronized between the memory controller bus and the SDRAM according to both the rising and falling edges of a bi-directional strobe signal (“DQS”). For example, during data writes to the SDRAM, data (“DQ”) writes are driven according to DQS. Similarly, during data reads, DQ is captured according to DQS. DQS is generated by the memory controller during write operations and by the SDRAM during read operations. By synchronizing data transfers according to both the rising and falling edges of DQS, DDR2 implementations allow for twice the data transfer rate than that provided by standard SDRAM without the need to increase the frequency of DQS.
Therefore, in light of the foregoing description, it is desirable to develop systems and methods for generating a DQS signal that only has edge transitions corresponding with DQ data transfer in source-synchronous DDR2 interface designs.